the inversion occurs in the B input leg; but in actual
use, it could occur in any leg of the AND gate.
The EXCLUSIVE OR operation differs from the
OR operation in the case where a signal is present at
every input terminal. In the OR, an output is produced;
in the EXCLUSIVE OR, no output is produced. In the
switching circuit shown, both switches cannot be
closed at the same time; but in actual computer
circuitry, this may not be the case. The accompanying
truth tables and block diagrams show two possible
circuit configurations. In each case the same final
results are obtained, but by different methods.
Basic Logic Diagrams
Basic logic diagrams are used to show the
operation of a particular unit or component. Basic
logic symbols are shown in their proper relationship
so as to show operation only in the most simplified
form possible. Figure 6-24 shows a basic logic
diagram for a serial subtractor. The operation of the
unit is described briefly in the next paragraph.
In the basic subtractor in figure 6-24, assume you
want to subtract binary 011 (decimal 1) from binary
100 (decimal 4). At time Io, the 0 input at A and 1 input
at B of inhibitor I1 results in a 0 output from inhibitor
I1 and a 1 output from inhibitor I2. The 0 output from
I1 and the 1 output from I2 are applied to OR gate G1,
producing a 1 output from G1. The 1 output from I2 is
also applied to the delay line. The I output from G1
along with the 0 output from the delay line produces
1 output from I3. The 1 input from G1 and the 0 input
from the delay line produce a 0 output from inhibitor
I4. The 0 output from L and the 1 output from I3 are
applied to OR gate G2 producing a 1 output.
At time t1 the 0 inputs on the A and B input lines
of I1 produce 0 outputs from I1 and I2. The 0 inputs on
both input lines of OR gate G1 result in a 0 output from
G1. The I input applied to the delay line at time to
emerges (1 bit time delay) and is now applied to the
inhibit line of 13 producing an 0 output from I3. The 1
output from the delay line is also applied to inhibitor
I4, and along with the 0 output from G1 produces a 1
output from I4. The I4 output is recycled back into the
delay line, and also applied to OR gate G2. As a result
of the 0 and 1 inputs from I3, and I4, OR gate G2
produces a 1 output.
At time t2, the 1 input on the A line and the 0 input
on the B line of I1 produce a 1 output from I1 and a 0
output from I2. These outputs applied to OR gate G1
produce a 1 output from G1, which is applied to 13 and
I4. The delay line now produces a 1 output (recycled
in at time t1), which is applied to I3 and I4. The 1 output
from the delay line along with the 1 output from G1
produces a 0 output from I3. The 1 output from G1
along with the 1 output from the delay line produces
a 0 output from I4. With 0 outputs from I3 and I4, OR
gate G2 produces a 0 output.
Detailed Logic Diagrams
Detailed logic diagrams show all logic functions
of the equipment concerned. In addition, they also
include such information as socket locations, pin
numbers, and test points to help in troubleshooting.
The detailed logic diagram for a complete unit may
consist of many separate sheets, as shown in the note
on the sample sheet in figure 6-25.
All input lines shown on each sheet of a detailed
logic diagram are tagged to show the origin of the
inputs. Likewise, all output lines are tagged to show
Figure 6-24.—Serial subtractor, basic logic diagrams.
6-24
